This application claims the priority benefit of Taiwan application serial no. 88117961, filed Oct. 18, 1999.
1. Field of the Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates to a method of planarizing a polysilicon plug by etching.
2. Description of the Related Art
As the level of integration of integrated circuit increases, sufficient surface area may not be available to accommodate all necessary interconnects. Hence, two or more metallic layers are usually formed. Functionally powerful products such as a microprocessor may even have four or five layers of metallic layers over a silicon chip.
In general, the fabrication of multi-level interconnects starts after MOS transistors are formed. Hence, multi-level interconnect fabrication can be regarded as an independent semiconductor process. To prevent the short-circuiting of the metal lines in a first metallic layer and the metal lines in a second metallic layer, metallic layers are isolated from each other by a dielectric layer. The dielectric layer is often referred to as an inter-metal dielectric layer.
FIGS. 1A and 1B are schematic cross-sectional views showing the process of planarizing a conventional polysilicon plug. A first metal line 101, a plug 104 (not completely formed yet) and an inter-metal dielectric layer 100 are shown in FIG. 1A. Here, the plug 104 is made from polysilicon. The polysilicon plug 104 is only partially formed because a layer of polysilicon material still covers the inter-metal dielectric layer 100 at the top of the plug 104. The layer of polysilicon material needs to be removed by planarization.
As shown in FIG. 1A, after polysilicon material is deposited into the opening 102 to form the polysilicon layer 104, the upper surface of the polysilicon layer 104 is rugged. Recesses 105 are normally formed in regions above the openings 102.
To remove the recesses 105 from the polysilicon layer 104, the polysilicon layer is planarized using a high-density plasma etching station. After an etching operation, a structure as shown in FIG. 1B is formed. As shown in FIG. 1B, recesses 105a are seen in the polysilicon layer 104a near the mouth of the openings 102. The central portion of these recesses 105a is at a level much lower than at the two corner regions. Moreover, the top surface of the polysilicon layer 104a formed by the aforementioned etching back step is at a level slightly below the top surface of the inter-metal dielectric layer 100. In other words, a portion of the polysilicon near the top of the polysilicon plug is permanently removed in addition to the recesses 105a at the top.
The invention provides a method of planarizing a polysilicon plug. An interconnect structure having a dielectric layer thereon is provided. The dielectric layer has an opening. Polysilicon is deposited into the opening such that the opening is overfilled. A recess is formed on the upper surface of the polysilicon layer above the opening. Planarization of the polysilicon plug is carried out by depositing a high molecular weight sacrificial film over the polysilicon layer such that the recess is entirely filled. The sacrificial film and the polysilicon layer are etched back to remove the sacrificial film and the polysilicon layer above the dielectric layer outside the opening. The polysilicon layer that remains inside the opening becomes a fully planarized polysilicon plug. The present invention thus provides a polysilicon plug with a flat top surface.
The high molecular weight sacrificial film is preferably deposited inside an inductive coupled plasma etcher that can produce high-density difluoromethane (CH2F2) plasma at a rate of about 10 to about 50 sccm.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.